Marjan Karkooti
Technical Advisor
Intellectual Property Law
3040 Post Oak Boulevard
Suite 1500
Houston, TX 77056
Phone: 713.623.4844
Fax: 713.623.4846
Direct Line: 713.577.4821
Email: mkarkooti@pattersonsheridan.com
Profile
Marjan Karkooti joined the firm in January 2009 as a technical advisor with a specialty in wireless communications and hardware design. Prior to joining the firm, Marjan was a research assistant in the Electrical and Computer Engineering department at Rice University while earning her M.S. and PhD. degrees. Most recently, she worked on a project funded by Nokia and NSF and designed a cooperative communication system utilizing distributed decoding. She has also designed flexible LDPC encoder/decoder architectures using FPGAs and ASIC. Marjan was an intern at Xilinx Inc. in San Jose where she designed an architecture for matrix inversion using QRD-RLS algorithm for OFDM systems. Marjan is proficient in a host of system and hardware design tools supporting DSPs, FPGAs and ASIC.
Education
- Ph.D., Computer Engineering, Rice University, 2009
- M.S., Computer Engineering, Rice University, 2004
- M.S., Socio-economic Systems Engineering, Institute for Research in Planning and Development, Tehran, Iran, 2000
- B.S., Electrical and Control Systems Engineering, Sharif University of Technology, Tehran, Iran, 1997
Practice Areas
Publications/Speeches/Presentations
- M. Karkooti and J. R. Cavallaro,"Cooperative Communications Using Scalable, Medium Block-length LDPC Codes". IEEE Wireless communication and networking conference. WCNC 2008
- M. Karkooti and J. R. Cavallaro,"Distributed Decoding in Cooperative Communications". IEEE Forty-First Asilomar Conference on Signals, Systems, and Computers. Nov 2007
- M. Karkooti, P. Radosavljevic, and J. R. Cavallaro,"Configurable LDPC Decoder Architectures for Regular and Irregular Codes". The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology,Jan 2007
- Y. Sun, M. Karkooti and J. R. Cavallaro, "VLSI Decoder Architecture for High Throughput, Variable Block-Size and Multi-Rate LDPC Codes". IEEE International symposium on Circuits and Systems (ISCAS 2007)
- Y.Sun, M. Karkooti and J. R. Cavallaro,"High Throughput, Parallel, Scalable LDPC Encoder/Decoder Architecture for OFDM Systems" Fifth IEEE Dallas Circuits and Systems Workshop: Design, Application, Integration and Software. Oct 2006
- M. Karkooti, P. Radosavljevic, and J. R. Cavallaro, "Configurable high throughput irregular LDPC decoder architecture: tradeoff analysis and implementation"17th IEEE International Conference on Application-specific Systems Architectures and Processors (ASAP),2006
- P.Radosavljevic, A. de Baynast, M. Karkooti, and J. R. Cavallaro, "Multi-rate high-throughput LDPC decoder: tradeoff analysis between decoding throughput and area,17th IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC), 2006
- P.Radosavljevic, A. de Baynast, M. Karkooti, and J. R. Cavallaro, "High-throughput multi-rate LDPC decoder based on architecture-oriented parity check matrices"14th European Signal Processing Conference (EUSIPCO), 2006
- M. Karkooti, J. Cavallaro, C. Dick, FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm, IEEE Asilomar Conference on Signals, Systems, and Computers, 2005
- M. Karkooti and J. Cavallaro, Semi-parallel Reconfigurable Architectures for Real-time LDPC Decoding, International Conference on Information Technology(ITCC), 2004
